Minutes of the weekly Otis and Beetle meeeting, 31.01.2002 >>14:00<<
ASIC lab meeting room.

Participants:
Harald Deppe, Sven Loechner, Michael Schmelling, Daniel Baumeister,
Ulrich Trunk, Uwe Stange


OTIS:
=====

1. Status of the Otis control logic tes (U.S.)

Simulation of pipeline control resulted in a minor redesign of the
latency circuit.
Readout control circuit is currently under simulation with special
emphasis on debugging and timing.

A Code review will be held for these parts on Fr. 08.02.02, 10:00 in the
ASIC lab.
A timing diagram of the control circuit schould also be presented at
that time.

Debugging features included on Otis 1.0:

W0 & R0 pipeline write and read pointers
WD0 & WR0 derandomizer write and read pointers
STB & STS self-test busy & self-test status
DbufEmpty & DbufFull monitors
ROstart & ROstop monitors
These signals will be assigned to a pair of pads via an I2C programmable
MUX.

Timing monitors for the memory control will be included on Otis 1.0

2. Status of DLL, decoder and layout (H.D.)

First channel complete, 3 next under construction. Timer block (to
achieve a 5ns setup time) is ready.

3. Summary of the OTR-Meeting (U.T.)
Mainli mechanical issues were discussed, esp. contacting the straw
tubes.

It was agreed that the  proposed reset schema as well as the readout
modes are usefull and should be implemented. It schould also be
presented to the collaboration during an LHCb week. A watchdog driven
DLL reset was proposed.

Reset of                                Otis 1.0        Specification
Registers                               POR             POR
DLL                                     Reset           I2C, Watchdog
BX-Counter                              Reset           I2C, Reset1, Reset2
Trigger Counter                         Reset           I2C, Reset1, Reset2
State Machines (Pipeline & Readout)     Reset           I2C, Reset1

4. Test of the derandomizer buffer (H.D & U.S)
There are now two test boards available, but due to their poor quality
(open circuits due to bad soldiering) no progress has been made up to
now.

Beetle:
=======

1. Beetle 1.1 measurements (D.B)
Daniel is still investigating the pipeline (collumn) and channel2channel
variations of pedestals and gains. There is no evidence for their
origin. He hopes to present some results at the FE-workshop on
07.02.2002.

2. Beetle FE 1.1 measurements (S.L)
Set 2E:
Gain: 38..55mV/MIP
ENC 869e+40,2e/pF
Problems with BG-setup @ NIKHEF have been solved.
Sven will send around a parameter list for the FE chips soon.
He will also present more ENC measurements at the FE-workshop.


Ulrich Trunk
--
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AAAAAAAH HH                                           Dr. Ulrich Trunk
AA    AH HH        Physikalisches Institut der Universitaet Heidelberg
AA LL AH HH                                      ASIC Labor Heidelberg
AA LL AH HH   Tel:   +49 6221 544324               Schroederstrasse 90
AA LL AH HH   Fax:   +49 6221 544345                D-69120 Heidelberg
   LL         mailto:[log in to unmask]
AA LLLLLLLL   http://wwwasic.kip.uni-heidelberg.de/~trunk/
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