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May 2003

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Subject:
From:
Ulrich Trunk <[log in to unmask]>
Reply To:
Mailing list for the users of the OTIS chip <[log in to unmask]>
Date:
Tue, 13 May 2003 15:31:04 +0200
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Minutes of the weekly Tracking Detector Readout Electronics Meeting,
8.5.2003 >>14:00<< seminar room 02.107.

Participants:
Daniel Baumeister, Sven Loechner, Harald Deppe, Uwe Stange, Ulrich Trunk

OTIS:
DNL (Uwe)
A measurement of the DNL was performed with the "patch 2" OTIS chip. For
that, DG2020, AWG and a LA(8k depth, GPIB readout) were employed. Since
the sweep of the fine time crosses the boundry of two BX, two triggers
have to be issued and the results have to be re-sorted. DAQ via GPIB is
still far to slooooooooow (1d5h for 16k hits). Thus the preliminary
results for the DNL (64bins: DNL=1.4 LSB and 32bins: DNL=0.8 LSB) are
limited by statistics.

A new setup will be much faster by using an FPGA instead of the LA.

OTIS 1.1 (Harald)
Pre-Pipeline logic will be removed from the TDC-channels and placed as a
block below the TDC. Routing from the channels to this block on Mz or a
M2-Mz stack is under investigation (C/l is 40% higher for a Mz-M2 stack
and 16% higher for staggered Mz-M2 lines than for a pure Mz routing.
However, the long lines from the "right" channels of the TDC carry the
signals of the first half of a BX, which relaxes timing constraints a
bit.

A specification change for the minimum hit distance (30ns) requires a
change in the priority encoding of the BX-phases: First phase requires
preority, while discarding the seconde one if both show a hit.

Beetle

Dip in readout figure (Sven)
Simulation with a resistor string in the shaper power supply reproduces
a dip in the readout figure, very similar to the measurement on Beetle
1.1 and 1.2, but with a smaller amplitude.

Series resistance in the buffer pwr supply has no effect, for the mux
this is still under investigation, but no effect is also expected, since
the output voltage of a forced-biased source follower does not depend on
the pwr supply. This has been proven for the buffer.

Beetle Probecard (Sven)
The probecard has been connected without the motherboard, which is not
yet ready. The test will be conducted using a DG2020 and monitoring the
digital signals and the 8 analogue output signals. A fist test shows,
that the card fits the Beetle's pad positions.

BEETLE 1.3 Layout
Hans verkoojen will come to Heidelberg 13-16.05.2003 to include the new
comparator

80MHz X-talk (Daniel)
A closer Look into the Beetle's clock trunk shows:
Beetle 1.1 ~  20 Clk-Buffers
Beetle 1.2 ~ 275 Clk-Buffers
OTIS 1.0   ~  80 Clk-Buffers
For Beetle 1.2 the Clk fan-out is very low (3 or 4) for many branches.
this will be raised to more reasonable values on Beetle 1.3.

Sticky charge (Daniel)
One chip has been patched with an external connection to the Pipeamp's
T/H signal. moving the T/H signal wrt. the Pipeamp reset removes the
sticky charge problem. This was also reproduced by sweeping the phase ot
the T/H signal wrt. Pipeamp reset.

Regards

Ulrich
--
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AAAAAAAH HH                                           Dr. Ulrich Trunk
AA    AH HH        Physikalisches Institut der Universitaet Heidelberg
AA LL AH HH                                      ASIC Labor Heidelberg
AA LL AH HH   Tel:   +49 6221 549150           Im Neuenheimer Feld 227
AA LL AH HH   Fax:   +49 6221 549259                D-69120 Heidelberg
   LL         mailto:[log in to unmask]
AA LLLLLLLL   http://wwwasic.kip.uni-heidelberg.de/~trunk/
----------------------------------------------------------------------

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