This is a List for the OTIS1.1 (new features, bugs to be fixed,
                                new ideas, ...)
Feel free to extend!!!


TDC-Core:
=========

1. Build in Comparators for generating the DLL Lock-State bit
2. DLL Reset have to be independent of external notReset-Signal
3. If necessary: arrange the DLL Delay elements in one line
                 to save space & routing


Fast Control:
=============

1. additional "2nd" readout mode have to be implemented
2. SEU robust Logic (triple redundent self-trig. latches from Beetle)


Slow Control:
==============

1. Build in the SEU robust I2C-Interface (from Beetle)
2. Boundary-Scan via I2C


Read-Out:
=========

1. Read the pipeline per I2C
2. The data output Pads (8bits) have to changed to single-ended CMOS level
3. Read-Out of Derandomizing-Buffer has to be changed (using D-Buffer
   Output as Latch - no additional latches in control-logic anymore)


A.O.B. :
========

1. The Voltage-DAC's for the ASD-X must be able to provide currents
   up to 600uA
2. Self-test for memory has to be changed (no chequerboard pattern)
3. Import the memory to SE to save routing work








Regards,
        Harald



********************************************************************************

    Harald Deppe
    University of Heidelberg
    Kirchhoff-Institut for Physics
    ASIC Laboratory
    Schroederstr. 90
    69120 Heidelberg


    Off.: +49 6221 54-4957
    Lab.: +49 6221 54-4355
    Fax : +49 6221 54-4345


    E-Mail: [log in to unmask]

********************************************************************************