Minutes: TDREM 20.06.2002, 14:00

Participants: Ulrich Trunk, Ulrich Uwer, Daniel Baumeister, Sven Loechner,
Harald Deppe, Uwe Stange, Andre Srowig

Beetle:
    Sven:
        level problem: no commercial bus master forr 2.5volts->
        radiation hard levelshifter and bi-directional repeater are
        needed for the slow control of beetle
        ->check with Paolo Moreira for 5V pad
        no new measurements of SCTA VELO, but yield problems
        due to long metal lines
    Daniel:
        radiation test of Beetle SR at Tandem accelerator @ MPI
        test of two chips
        I2C bus scan andparity check in pipeline
        preliminary result: about 100 SEU/h
        Instability / sensitivity of the setup not understood

Otis:
    Harald:
        TDC-core
            comparators for DLL lock state bit
            DLL reset signal independent
            DLL layout in one line to save space and routing
        fast control
            2nd readout mode I2C-interface
            boundary scan
        AOB
            voltage DACs must provide 600uA for ASD-x
            self test, memory ( no chequerboard)
        readout
            data out -> single ended
            use DBuffer latch instead additional latch at DBuffer data out

            pipeline read access per I2C

IBM .25:
    Ulrich:
            New Design Kit (1.0.3)
        - only supports Cadence 4.4.3
        - 4.46 will be supported when available later this year
        - New pads with ESD protection (Name: xxx_ESD)
        - Slew rate controlled outputs (Name: xxxSxxx)
        - 3.3/5V compatible I/O pads available from Paolo Moreira upon
request
        - Protection diodes available as single instances

        - ESD Design Kit
                - Documentation available on
http://deepsub.web.cern.ch/deepsub/
                - Tested for electrical but not ESD functionality

        - Sim models again up to date with IBM
        - DRC rules: density check improved (local filling rules), take
care on
        your own!
        - CERN has >1 Hercules license
         - Format converter Hercules -> Cadence Marker available

        Common Cell library
    - don't reinvent the wheel.....
        - write 1/2 page of description on everything that might be of
interest
        for others...
        - CERN bandgap reference has problems >1Mrad dose due to leakage
        currents
                - will be corrected
        - 40MHz dual ported SRAM macro block

        Yield Experience
        BAD ONES
        APV25           7x8             20-80%  consistent per wafer lot
        HAL25           4x11            ~50%    probably due to long metal
lines
        AtlasPix1       11x7.5          15%     (5 met) now much better
(80%)
        Atlas RoC       6x4                     (5 met) Same run as
AtlasPix1, yield strongly
        correlated
        GOOD ONES
        CMS             6x6, 2x2        >90%    after packaging
        HPTDC           6.5x6.5         80-90%  prototype & engineering
run
        AtlasPixel      14x14           >50%
        SCAC (Nevis Lab)                90%

        - MPW to production is not a smooth ride
        - Very large handcrafted designs are unusual in industry
        - 1st level of failure analysis is cheap (10kEUR) @ IBM
        - Failure of different chips might be different phenomena
        - DRC rules in the manual are not sufficient for our designs

        IMMEDIATE HELP
        - add protection diodes to long lines (0.18 & 0.13 have'em on
every
        std. cell!!!)
        - increase junction area of transistors driving long lines
        - add testability features
        - be conservative!!!

        - no handle on yield in contract
        - commercial products in this process are usually a few % above
the
        expected yield
        - IBM tries to track down the yield problem to a common
station/machine
        in the line

        Frame Contract
        - covers up to 12Mio SFR, from which at max. 30% can originate
from
        CERN
        - Ends 1. March 2004, but will be extended

        Other stuff:
        - Calibre rules for CMOS6SF exist (I will try to get them)
        - Package info (chip, pkg & quantity) should be sent to Sandro
        - IBM offers Fuses for $20/wafer, which can be laser-blown by IBM
        - Only 2 wafers guaranteed per engineering run
        - Packaging of the chips only in the EU, US & JP
        - MC simulation tool: RAL has a script to do this outside Cadence

Dune:
    Andre
        charge amp noise (AMS) of 200 electrons factor two higher than
        discrete jFET amp
        -> verify measurement, consider .13u / .18u process
        on trigger -> readout of complete pipeline -> bootle neck ->
storage
        time of dynamic analog memory cell up to 1.2ms -> estimate error
        due to leakage currents
        alternative solutions:
            run ADC at input and store digitally -> check powerconsumption
of ADC
            digital DBuffer with size of analog pipeline -> overkill


Ulrich Trunk schrieb:

> Agenda of the weekly Tracking Detector Readout Electronics Meeeting,
> 20.06.2002 >>14:00<< ASIC lab meeting room.
>
> Beetle:
>         Report fom Lausanne review meeting              S.L.
>         First impressions from SEU test                 D.B.
>
> Otis:
>         New features for Otis 1.1                       H.D.
>         Manpower issues                                 all
>
> IBM 0.25:
>         Report from London                              U.T.
>         I2C Repeater                                    all
>
> Dune:
>         Report from meeting @ MPI                       A.S.
>
> AOB