Sorry fuer die Verspaetung!
Hier die Minutes:

OTIS:
=====

1) All channels/hitregs finished, but no overall LVS yet.
   Next steps: power/channel routing.
   Comparators for Vctrl will only be implemented if there's
   enough time left.
   Loopfilter will not be changed.

2) First chip size estimate: 6000um x 5000um

3) Ulrich Trunk will have a look at the behavioral model of
   DBufferFull in the testbench of the control algorithm.

Beetle:
=======

1) Daniel finished work on SlowControl, which now includes
   the bias registers and the triple redundant self triggered
   flip flops.
   Next steps: fast control.

2) Sven is now working on frontend bias registers.
   Next steps: include comparator, multiplexer and (with low
   priority) the probe pads.

3) Chip size: 5100um x 6100um


Gruesse,
        Uwe

--
Uwe Stange                 http://www.uwe-stange.de
Physikalisches Institut der Universitaet Heidelberg
c/o Kirchhoff-Institut fuer Physik, ASIC Labor,
    Schroederstr. 90, 69120 Heidelberg,  Tel: 06221/544357
    http://wwwasic.kip.uni-heidelberg.de/lhcbot/about.html